The present invention relates to a method of producing an insulated gate bipolar transistor ("IGBT") or a vertical insulated gate field effect transistor.
FIG. 3 is a sectional view showing the structure of an IGBT having an N-type channel element. Such an IGBT includes a P.sup.+ substrate 1, a high-resistance N.sup.- layer 2, a P.sup.+ region 3, a P-type base layer 4, a high-impurity-density P.sup.++ layer 5, an N.sup.+ source region 6, a gate oxide film 7, a polycrystalline silicon gate 8, a PSG insulation layer 9, a source electrode 10, a gate electrode 11, and a drain electrode 12. The symbols S, G and D represent the terminals of a source, a gate and a drain, respectively.
As shown in FIG. 3, an IGBT fundamentally has a four-layer structure of PNPN although NPNP types can also be made. The operation thereof will now be explained with reference to an equivalent circuit shown in FIG. 4. In this circuit, a PNP transistor 13 and an NPN transistor are connected to each other as shown in FIG. 4, and has a resistance (Rp) 15. The transistor 14 is equivalent to an NPN parasitic transistor consisting of the N.sup.- layer 2, the P-type base layer 4 and the N.sup.+ layer 6 shown in FIG. 3. It is generally possible to control the main current by a gate 16, but if the resistance (Rp) 15 is large, a potential difference of more than a predetermined voltage is produced between the base and the emitter of the transistor 14, and a current flows between the collector and the emitter, thereby actuating the transistor 14. As a result, even after the gate 16 is cut off, the main current continues to flow, resulting in the breakage of the element itself. This phenomenon is called latchup. In order to actuate the IGBT normally, it is necessary to fabricate an element which does not cause latchup.
It is well known that the P.sup.++ layer 5 is formed to prevent latchup, as shown in FIG. 3. The P.sup.++ layer 5 is provided in order to reduce the resistance (Rp) 15 in FIG. 4, and to reduce the potential difference between both ends of the resistance 15 and lower the voltage between the emitter and the base, thereby preventing the parasitic transistor 14 from being actuated.
The operation of the P.sup.++ layer 5 will be explained in relation to the prevention of latchup with reference to FIG. 5, which is a partially enlarged view of the IGBT shown in FIG. 3. The same reference numerals are provided for the elements which are the same as those in FIG. 3. In FIG. 5, a channel is formed by induction in the base layer 4, specifically in the portion thereof indicated by the reference numeral 17 to connect the source region 6 and the high-resistance layer 2. The direction in which electrons flow through this channel is indicated with the arrow 18 of a solid line and the direction in which holes flow is indicated with the arrow 19 of a broken line. When holes flow along the route indicated by the arrow 19, a potential difference is produced by the resistance Rp at that time. In order to limit the potential difference to a low value, the high-density P.sup.++ layer 5 is preferably as close to the channel 17 as possible. The reference letters A, B, C and D in FIG. 5 represent various possible end positions of the P.sup.++ layer 5 for comparison. The merits and demerits of the positions will be described in the following.
For example, if the P.sup.++ layer is diffused to the position A, the channel 17 would be lost because the P.sup.++ layer 5 would surround the D source region 6, thereby making the operation of the MOS impossible. On the other hand, if the P.sup.++ layer is diffused only to the position D, since the holes 19 pass through the high-resistance P layer 4 for a longer time, the voltage drop is increased, so that latchup is apt to be produced. In addition, since a P.sup.+ well 3 is ordinarily formed, diffusion of the P.sup.++ layer 5 to the position D produces little effect. Diffusion of the P.sup.++ layer 5 to the position B is the most effective and ideal. However, controlling the diffusion so as to set the end of the P.sup.++ layer 5 at the position B is difficult and involves a fair possibility of diffusing the P.sup.++ layer 5 to the position A due to positional deviation produced by one cause or another. Thus it lacks in stability in the manufacturing process. For the above reasons, it is appropriate to diffuse the P.sup.++ layer 5 to the position C, i.e., substantially in alignment with the polysilicon gate 8, in order to prevent latchup. To realize this, in the present state of art, a mask such as a resist is generally used at the step of producing the P.sup.++ layer 5 in the fabrication of an IGBT.
As described above, it is important for preventing latchup to bring the high-density P.sup.++ layer as close to the position (2) in FIG. 5 as possible in the fabrication of an IGBT. It is therefore necessary to position a mask very accurately. The N.sup.+ source layer 6 is ordinarily formed by ion implantation with the polysilicon gate 8 as a mask, so that it is self aligned with the gate, thereby obtaining a good accuracy. However, when the P.sup.++ layer 5 is formed by using a different mask, it is necessary to compensate for deviation. Therefore, it is necessary to design the mask at a position closer to the position (4), which is behind the target position (3). In this way, the prior art, in which the P.sup.++ layer 5 is formed by diffusion using a mask, has various inconveniencies.
Accordingly, it is an object of the present invention to eliminate the above-described problems in the prior art and to provide a method of producing an IGBT with a good efficiency which prevents latchup by forming a high-impurity density P.sup.++ region by diffusion and self alignment without using a mask to define the outer boundaries of the region with a high accuracy in place of a conventional method in which the high-density P.sup.++ layer is formed by using a mask.